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ZL30416 SONET/SDH Clock Multiplier PLL
Data Sheet Features
* Low jitter clock outputs suitable for OC-192, OC48, OC-12, OC-3 and OC-1 SONET applications as defined in Telcordia GR-253-CORE Low jitter clock outputs suitable for STM-64, STM16, STM-4 and STM-1 applications as defined in ITU-T G.813 Provides one differential LVPECL output clock selectable to 19.44, 38.88, 77.76, 155.52 or 622.08 MHz Provides a single-ended CMOS output clock at 19.44 MHz Accepts a single-ended CMOS reference at 19.44 MHz or a differential LVDS, LVPECL or CML reference at 19.44 or 77.76 MHz Provides a LOCK indication 8 mm x 8 mm CABGA package 3.3 V supply Ordering Information ZL30416GGG 64 Ball CABGA
November 2004
*
-40C to +85C
*
Description
The ZL30416 is an Analog Phase-Locked Loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30416 generates low jitter output clocks suitable for Telcordia GR-253CORE OC-192, OC-48, OC-12, OC-3, and OC-1 and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 applications. The ZL30416 accepts a CMOS compatible reference at 19.44 MHz or a differential LVDS, LVPECL or CML reference at 19.44 or 77.76 MHz and generates a differential LVPECL output clock selectable to 19.44, 38.88, 77.76, 155.52 or 622.08 MHz and a singleended CMOS clock at 19.44 MHz. The ZL30416 provides a lock indication.
* *
* * *
Applications
* SONET/SDH line cards
REF_SEL
LPF
FS3 FS2 FS1
C19o, C38o, C77o, C155o, C622o, LVPECL output
C19i Reference Selection MUX
Frequency & Phase Detector
Loop Filter
VCO
REFinP/N
19.44 MHz and 77.76 MHz State Machine Reference and Bias Circuit
Frequency Dividers and Clock Drivers
OC-CLKoP/N
C19o
C19i or C77i CML, LVDS, LVPECL input
REF_FREQ
LOCK
BIAS
VCC
GND
VDD
C19oEN
Figure 1 - Functional Block Diagram
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Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30416
Data Sheet
1 1
2
3
4
5
6
7
8
A
NC NC NC OC-CLKoP OC-CLKoN GND NC NC
B
NC NC VCC1 GND NC GND GND VCC
C
GND VCC2 GND GND GND NC VDD GND
D
BIAS LPF NC GND VCC VCC GND GND
E
LOCK NC NC FS2 VCC VDD NC REFinN
F
NC NC REF_FREQ C19oEN C19i C19o GND REFinP
G
GND VDD REF_SEL FS3 GND GND VDD VDD
H
NC NC NC VDD FS1 VDD GND GND
1
- A1 corner is identified by metallized markings. 8 mm x 8 mm Ball Pitch 0.8mm
Figure 2 - BGA 64 Ball Package (Top View)
1.0
Ball Description
Ball Description Table Ball # A1, A2 A3 A4 A5 Name NC OC-CLKoP OC-CLKoN Description No internal bonding Connection. Leave unconnected. SONET/SDH Clock (LVPECL Output). These outputs provide a selectable differential LVPECL clock at 19.44 Hz, 38.88 MHz, 77.76 MHz, 155.52 MHz, and 622.08 MHz. The output frequency is selected with FS3, FS2 and FS1 inputs. Ground. 0 volt No internal bonding Connection. Leave unconnected. Positive Analog Power Supply. +3.3 V +/-10% Ground. 0 volt No internal bonding Connection. Leave unconnected. Ground. 0 volt
A6 A7, A8 B1, B2 B3 B4 B5 B6, B7
GND NC VCC1 GND NC GND
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Ball Description Table (continued) Ball # B8 C1 C2 C3, C4 C5 C6 C7 C8 D1 D2 D3 D4 D5, D6 D7, D8 E1 E2, E3 G4 E4 H5 E5 E6 E7 E8 F8 Name VCC GND VCC2 GND NC VDD GND BIAS LPF NC GND VCC GND LOCK NC FS3 FS2 FS1 VCC VDD NC REFinN REFinP Description Positive Analog Power Supply. +3.3 V 10% Ground. 0 volt Positive Analog Power Supply. +3.3 V 10% Ground. 0 volt No internal bonding Connection. Leave unconnected. Positive Digital Power Supply. +3.3 V 10% Ground. 0 volt Bias Circuit.
Data Sheet
External Low-Pass Filter (Analog). Connect external RC network for the lowpass filter. No internal bonding Connection. Leave unconnected. Ground. 0 volt Positive Analog Power Supply. +3.3 V 10% Ground. 0 volt Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to the selected input reference. No internal bonding Connection. Leave unconnected. Frequency Select 3-1 (CMOS Input). These inputs select the clock frequency on the OC-CLKo output. The possible output frequencies are: 19.44 MHz (000), 38.88 MHz (001), 77.76 MHz (010), 155.52 MHz (011), 622.08 (100) Positive Analog Power Supply. +3.3 V 10% Positive Digital Power Supply. +3.3 V 10% No internal bonding Connection. Leave unconnected. Differential Reference Clock Input (CML/LVDS/LVPECL Compatible Input). These inputs accept a differential clock at 77.76 MHz or 19.44 MHz as the reference for synchronization. These inputs do not have on-chip AC coupling capacitors. No internal bonding Connection. Leave unconnected. Reference Frequency (CMOS Input). This input selects the rate of the differential input clock (REFinP/N) to be either 77.76 MHz or 19.44 MHz. C19o Output Enable (CMOS Input). If tied high this control input enables the C19o output clock. Pulling this pin low forces the output driver into a high impedance state. C19 Reference Input (CMOS Input). This is a single-ended input reference source used for synchronization. This input accepts 19.44 MHz.
F1, F2 F3 F4
NC REF_FREQ C19oEN
F5
C19i
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Ball Description Table (continued) Ball # F6 F7, G1 G2 G3 Name C19o GND VDD REF_SEL Description
Data Sheet
Clock 19.44 MHz (CMOS Output). This output provides a single-ended CMOS clock at 19.44 MHz. Ground. 0 volt Positive Digital Power Supply. +3.3 V 10% Reference Select (CMOS Input). If tied low then the C19i single-ended reference is used as the input reference source. If tied high then the REFinP/N differential pair is used as the input reference source. See E4 ball description. Ground. 0 volt Positive Digital Power Supply. +3.3 V 10% No internal bonding Connection. Leave unconnected. Positive Digital Power Supply. +3.3 V 10% See E4 ball description. Positive Digital Power Supply. +3.3 V 10% Ground. 0 volt.
G4 G5, G6 G7, G8 H1, H2 H3 H4 H5 H6 H7, H8
FS3 GND VDD NC VDD FS1 VDD GND
2.0
Functional Description
The ZL30416 is an analog phased-locked loop which provides rate conversion and jitter attenuation for SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the ZL30416 is shown in Figure 1 and a brief description is presented in the following sections.
2.1
Reference Selection Multiplexer
The ZL30416 accepts two types of input reference clocks: differential: operating at 19.44 MHz or 77.76 MHz, compatible with LVDS/LVPECL/CML threshold levels single-ended: operating at 19.44 MHz, compatible with CMOS switching levels
The REF_SEL input determines whether the single-ended CMOS reference input (REFin) or the differential reference inputs (REFinP/N) are used as input reference clocks. The REF_FREQ input selects the rate of the differential input clock to be either 19.44 MHz or 77.76 MHz. See Table 1 for details.
REF_SEL 0 1 1
REF_FREQ x 0 1
Selected Input Reference C19i REFin REFin
Reference Frequency 19.44 MHz (CMOS) 77.76 MHz (Differential) 19.44 MHz (Differential)
Table 1 - Input Reference Selection
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2.2 Frequency/Phase Detector
Data Sheet
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback signal from the Frequency Divider circuit and provides an error signal equal to the frequency/phase difference between the two. This error signal is passed to the Loop Filter circuit.
2.3
Lock Indicator
The ZL30416 has a built-in LOCK detector that measures frequency difference between input reference clock C19i and the VCO frequency. When the VCO frequency is less than 300 ppm apart from the input reference frequency then the LOCK output is set high. The LOCK output is pulled low if the frequency difference exceeds 1000 ppm.
2.4
Loop Filter
The Loop Filter is a low-pass filter. This low-pass filter eliminates high frequency spectral components from a phase error signal produced by the Phase Detector. This ensures low output jitter that meets network jitter requirements. The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF ball and ground as shown in Figure 3.
ZL30416
Frequency and Phase Detector
LPF Loop Filter RF CF
RF=8.2 k, CF=470 nF fTYP=14.4 kHz
VCO
Figure 3 - Loop Filter Elements
2.5
VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter and based on the voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers and Clock Drivers" block that divides VCO frequency and buffer generated clocks.
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2.6 Frequency Dividers and Clock Drivers
Data Sheet
The output of the VCO feeds the high frequency clock to the "Frequency Dividers and Clock Drivers" circuit to provide one differential LVPECL compatible clock with selectable frequency and one single-ended 19.44 MHz C19o output clock. The C19o clock can be enabled or disabled with the associated C19oEN Output Enable ball. Internally, this block provides a feedback clock that closes the PLL loop. The frequency of the OC-CLKo differential output clock is selected with FS3, FS2 and FS1 inputs as is shown in the following table. FS3 0 0 0 0 1 1 1 1 FS2 0 0 1 1 0 0 1 1 FS1 0 1 0 1 0 1 0 1 OC-CLKo Frequency 19.44 MHz 38.88 MHz 77.76 MHz 155.52 MHz 622.08 MHz Reserved Reserved Reserved
Table 2 - OC-CLKo Clock Frequency Selection
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3.0 ZL30416 Performance
Data Sheet
The following are some of the ZL30416 performance indicators that complement results listed in the Characteristics section of this data sheet.
3.1
Input Jitter Tolerance
Jitter tolerance is a measure of the PLL's ability to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) in the presence of jitter applied to its input reference. The input jitter tolerance of the ZL30416 is shown in Figure 4. On this graph, the single line at the top represents the input jitter tolerance and the three overlapping lines below represent the specification for minimum input jitter tolerance for OC-192, OC-48 and OC-12 network interfaces. The jitter tolerance is expressed in picoseconds (pk-pk) to accommodate requirements for interfaces operating at different rates.
Figure 4 - Input Jitter Tolerance
3.2
Jitter Transfer Characteristic
Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a PLL. This ratio is expressed in dB and it characterizes the PLL's ability to attenuate (filter) jitter. The ZL30416 jitter transfer characteristic complies with the maximum 0.1 dB jitter gain specified in Telcordia's GR-253-CORE.
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4.0
4.1
Data Sheet
Applications
Generation of Low Jitter SONET/SDH Equipment Clocks
The functionality and performance of the ZL30416 complements the entire family of the Zarlink's advanced network synchronization PLL's. Its jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces operating up to OC-192/STM-64. The ZL30416 in combination with the MT90401 or the ZL30407 (SONET/SDH Network Element PLL's) provides the core building blocks for high quality equipment clocks suitable for network synchronization (see Figure 5).
REFinP/N
ZL30416
C19i LPF
REF_SEL REF_FREQ FS1 C19oEN FS3 LOCK FS2
622.08 MHz OC-CLKoP/N LVPECL 155.52 MHz 77.76 MHz 38.88 MHz 19.44 MHz C19o CMOS 19.44 MHz
CF RF
RF = 1 k CF = 470 nF
PRI SEC Synchronization Reference Clocks RefSel RefAlign PRIOR SECOR LOCK HOLDOVER
ZL30407
C19o C155o C34o/C44o C16o C8o C6o C4o C2o C1.5o F16o F8o F0o
CMOS LVDS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
19.44 MHz 155.52 MHz 34.368 MHz or 44.736 MHz 16.384 MHz 8.192 MHz 6.312 MHz 4.096 MHz 2.048 MHz 1.544 MHz 8 kHz 8 kHz 8 kHz
C20i
R/W A0 - A6
20 MHz OCXO
D0 - D7
DS CS
Data Port
uP
Controller Port
Note: Only main functional connections are shown
Figure 5 - SONET/SDH Equipment Clock
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4.2 4.2.1 4.2.1.1 Recommended Interface Circuit Interfacing to REFin Receiver Interfacing REFin Receiver to LVPECL Driver
Data Sheet
The ZL30416 REFin differential receiver can be connected to LVPECL compatible driver with an interface circuit, as shown in Figure 7. The R1s and R2s terminating resistors should be placed close to the REFin input balls.
ZL30416 VCC=+3.3V VDD/2
R1
Z=50 LVPECL Driver Z=50 R2
R1
Cc REFinP
Receiver
REFinN R2 Cc
Typical resistor values: R1 = 127 , R2 =82.5 Typical capacitor values: Cc = 0.1 F
Figure 6 - Interfacing to LVPECL Driver
4.2.1.2
Interfacing REFin Receiver to LVDS or CML Drivers
The ZL30416 REFin differential receiver can be connected to LVDS or CML driver with an interface circuit, as shown in Figure 7. The 100 terminating resistors should be placed close to the REFin input balls.
ZL30416
VDD/2 Z=50 100 Z=50 REFinN Cc Cc REFinP Receiver
LVDS or CML Driver
Typical capacitor values: Cc = 0.1 F
Figure 7 - Interfacing to LVDS or CML Driver
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4.2.2 4.2.2.1 Interfacing to OC-CLKo Output LVPECL to LVPECL Interface
Data Sheet
The OC-CLKo outputs provide differential LVPECL clocks at 622.08 MHz, 155.52 MHz, 77.76 MHz, 38.88 MHz and 19.44 MHz selectable with FS3, FS2 and FS1 frequency select inputs. The LVPECL output drivers require a 50 termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The terminating resistors should be placed close to the LVPECL receiver.
+3.3 V
Typical resistor values: R1 = 127 , R2 =82.5
0.1 uF ZL30416 VCC VCC=+3.3 V LVPECL Receiver
LVPECL Driver
OC-CLKoP
Z=50 Z=50
R1
R1
OC-CLKoN R2 GND R2
Figure 8 - LVPECL to LVPECL Interface
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4.3 Power supply and BIAS Circuit Filtering Recommendations
Data Sheet
Figure 9 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter performance. The level of required filtering is subject to further optimization and simplification. Please check Zarlink's web site for updates.
Ferrite Bead
0.1 uF 0.1 uF
10 uF
1 1
2
3
4
5
6
7
8
4.7 33 uF 220 33 uF 33 uF
A
NC NC NC OC-CLKoP OC-CLKoN GND NC NC
B
0.1 uF 0.1 uF
C
NC
NC
VCC1
GND
NC
GND
GND
VCC
GND
VCC2
GND
GND
GND
NC
VDD
GND
0.1 uF 0.1 uF
D
0.1 uF
E
BIAS
LPF
NC
GND
VCC
VCC
GND
GND
LOCK
NC
NC
FS2
VCC
VDD
NC
REFinN
0.1 uF 0.1 uF
F
NC NC REF_FREQ C19oEN C19i C19o GND REFinP
+3.3 V Power Rail
G
GND VDD REF_SEL FS3 GND GND VDD VDD
0.1 uF 0.1 uF 0.1 uF
H
NC NC NC VDD FS1 VDD GND GND
0.1 uF 0.1 uF
0.1 uF
0.1 uF
Notes: 1. All the ground pins (GND) are connected to the same ground plane. 2. Select Ferrite Bead with IDC > 400 mA and RDC in a range from 0.10 to 0.15 .
Figure 9 - Power Supply and BIAS Circuit Filtering
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5.0 Characteristics
Data Sheet
Absolute Maximum Ratings Characteristics 1 2 3 4 5 6 Supply voltage Voltage on any ball Current on any ball ESD rating Storage temperature Package power dissipation Sym. VDDR, VCCR VBALL IBALL VESD TST PPD -55 Min. TBD -0.5 -0.5 Max. TBD VCC + 0.5 VDD + 0.5 30 1250 125 1.0 Units V V mA V C W
Voltages are with respect to ground unless otherwise stated. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions Characteristics 1 2 Operating temperature Positive supply Sym. TOP VDD, VCC Min. -40 3.0 Typ. 25 3.3 Max. +85 3.6 Units C V Notes
Voltages are with respect to ground unless otherwise stated. Typical figures are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics Characteristics 1 2 3 4 5 Supply current CMOS: High-level input voltage CMOS: Low-level input voltage CMOS: Input leakage current CMOS: Input bias current for pulled-down inputs: FS1, FS2 and FS3 CMOS: Input bias current for pulled-up inputs: C19oEN CMOS: High-level output voltage Sym. IDD+ICC VIH VIL IIL IB-PU 0.7 VDD 0 1 300 Min. Typ. 185 VDD 0.3 VDD 5 Max. Units mA V V uA uA VI = VDD or 0 V VI = VDD Notes Note 1 Note 2
6 7
IB-PD VOH 2.4
90
uA V
VI = 0 V IOH = 8 mA
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DC Electrical Characteristics (continued) Characteristics 8 9 10 11 12 13 CMOS: Low-level output voltage CMOS: C19o output rise time CMOS: C19o output fall time LVPECL: Differential output voltage LVPECL: Offset voltage LVPECL: Output rise/fall times Sym. VOL TR TF IVOD_LVPEC LI VOS_LVPECL TRF Vcc1.38 1.8 1.1 1.30 Vcc1.27 260 Vcc1.15 Min. Typ. Max. 0.4 3.3 1.4 Units V ns ns V V ps
Data Sheet
Notes IOL = 4 mA 18 pF load 18 pF load for 622 MHz Note 2 for 622 MHz Note 2 for 622 MHz Note 2
Voltages are with respect to ground unless otherwise stated. Typical figures are for design aid only: not guaranteed and not subject to production testing. Supply voltage and operating temperature are as per Recommended Operating Conditions. Note 1: The ILVPECL current is determined by the external termination network connected to LVPECL outputs. More than 25% of this current (10 mA) flows outside the chip and it does not contribute to the internal power dissipation. The Supply Current value listed in the table includes this current to reflect total current consumption of the ZL30416 and the attached LVPECL termination network. Note 2: LVPECL outputs terminated with ZT = 50 resistors biased to VCC -2V (see Figure 8).
AC Electrical Characteristics - Output Timing Parameters Measurement Voltage Levels Characteristics 1 2 3 Threshold voltage Rise and fall threshold voltage high Rise and fall threshold voltage low Sym. VT-CMOS VT-LVPECL VHM VLM CMOS 0.5 VDD 0.7 VDD 0.3 VDD LVPECL 0.5 VOD_LVPECL 0.8 VOD_LVPECL 0.2 VOD_LVPECL Units V V V
Voltages are with respect to ground unless otherwise stated.
Timing Reference Points
All Signals
tIF, tOF tIR, tOR
VHM VT VLM
Figure 10 - Output Timing Parameter Measurement Voltage Levels
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AC Electrical Characteristics - C19i Input to C19o Output Timing Characteristics 1 C19i to C19o delay Sym. tC19D Min. 4.4 Typ. 6.7 Max. 9.4 Units ns
Data Sheet
Notes
Supply voltage and operating temperature are as per Recommended Operating Conditions. Typical figures are for design aid only: not guaranteed and not subject to production testing.
C19i (19.44 MHz) C19o (19.44 MHz) Note: All output clocks have nominal 50% duty cycle. tC19D
V T-CMOS
V T-CMOS
Figure 11 - C19i Input to C19o Output Timing
AC Electrical Characteristics - REFin to C19o Output Timings Characteristics 1 2 REFin (19.44 MHz) to C19o (19.44 MHz) delay REFin (77.76 MHz) to C19o (19.44 MHz) delay Sym. tR19OC19D tR77OC77D Min. 1.4 7.9 Typ. 7.8 9.9 Max. 10 13 Units ns ns Notes
tR19OC19D REFin (19.44 MHz) VT-LVPECL
REFin (77.76 MHz)
tRW
tR77OC77D VT-LVPECL
C19o (19.44 MHz)
VT-CMOS
Figure 12 - REFin Input to C19o Output Timing
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AC Electrical Characteristics - C19i Input to OC-CLKo Output Timing Characteristics 1 2 3 4 5 6 C19i(CMOS) to C19o(LVPECL) delay C19i(CMOS) to OC-CLKo(38) delay C19i(CMOS) to OC-CLKo(77) delay C19i(CMOS) to OC-CLKo(155) delay C19i(CMOS) to OC-CLKo(622) delay All Output Clock duty cycle Sym. tC19D tC38D tC77D tC155D tC622D dC Min. 1.4 1.2 0.9 0.6 0 48 Typ. 3.3 3.0 2.6 2.3 0.8 50 Max. 5.1 4.8 4.4 4.1 1.6 52 Units ns ns ns ns ns %
Data Sheet
Notes
Supply voltage and operating temperature are as per Recommended Operating Conditions. Typical figures are for design aid only: not guaranteed and not subject to production testing.
C19i (19.44 MHz) tC19D OC-CLKo(19) (19.44 MHz) tC38D OC-CLKo(38) (38.88 MHz) tC77D OC-CLKo(77) (77.76 MHz) tC155D OC-CLKo(155) (155.52 MHz)
VT-CMOS
VT-LVPECL
VT-LVPECL
VT-LVPECL
VT-LVPECL
tC622D OC-CLKo(622) (622.08 MHz) VT-LVPECL
Note: All output clocks have nominal 50% duty cycle.
Figure 13 - C19i Input to OC-CLKo Output Timing
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AC Electrical Characteristics - REFin (19.44 MHz) Input to OC-CLKo Output Timing Characteristics 1 2 3 4 5 REFin(19.44 MHz) to OC-CLKo(19) delay REFin(19.44 MHz) to OC-CLKo(38) delay REFin(19.44 MHz) to OC-CLKo(77) delay REFin(19.44 MHz) to OC-CLKo(155) delay REFin(19.44 MHz) to OC-CLKo(622) delay Sym. tC19-19D tC19-38D tC19-77D tC19-155D tC19-622D Min. 2.4 1.9 1.7 1.4 0 Typ. 4.3 4.0 3.7 3.4 0.8 Max. 6.2 6.0 5.6 5.3 1.6 Units ns ns ns ns ns
Data Sheet
Notes
Supply voltage and operating temperature are as per Recommended Operating Conditions. Typical figures are for design aid only: not guaranteed and not subject to production testing.
REFin (19.44 MHz) tC19-19D OC-CLKo(19) (19.44 MHz) tC19-38D OC-CLKo(38) (38.88 MHz) tC19-77D OC-CLKo(77) (77.76 MHz) tC19-155D OC-CLKo(155) (155.52 MHz)
VT-LVPECL
VT-LVPECL
VT-LVPECL
VT-LVPECL
VT-LVPECL
tC19-622D OC-CLKo(622) (622.08 MHz) VT-LVPECL
Note: All output clocks have nominal 50% duty cycle.
Figure 14 - REFin (19.44 MHz) Input to OC-CLKo Output Timing
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AC Electrical Characteristics - REFin (77.76 MHz) Input to OC-CLKo Output Timing Characteristics 1 2 3 4 5 REFin(77.76 MHz) to OC-CLKo(19) delay REFin(77.76 MHz) to OC-CLKo(38) delay REFin(77.76 MHz) to OC-CLKo(77) delay REFin(77.76 MHz) to OC-CLKo(155) delay REFin(77.76 MHz) to OC-CLKo(622) delay Sym. tC77-19D tC77-38D tC77-77D tC77-155D tC77-622D Min. 3.5 3.2 2.9 2.6 0 Typ. 6.5 6.2 5.9 5.6 0.8 Max. 9.5 9.2 8.8 8.6 1.6 Units ns ns ns ns ns
Data Sheet
Notes
Supply voltage and operating temperature are as per Recommended Operating Conditions. Typical figures are for design aid only: not guaranteed and not subject to production testing.
REFin (77.76 MHz) tC77-19D OC-CLKo(19) (19.44 MHz) tC77-38D OC-CLKo(38) (38.88 MHz) tC77-77D OC-CLKo(77) (77.76 MHz) tC77-155D OC-CLKo(155) (155.52 MHz)
VT-LVPECL
VT-LVPECL
VT-LVPECL
VT-LVPECL
VT-LVPECL
tC77-622D OC-CLKo(622) (622.08 MHz) VT-LVPECL
Note: All output clocks have nominal 50% duty cycle.
Figure 15 - REFin (77.76 MHz) Input to OC-CLKo Output Timing
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Performance Characteristics - Functional - (VCC = 3.3 V 10%; TA = -40 to 85C) Characteristics 1 Pull-in range Min. 1000 Typ. Max. Units ppm
Data Sheet
Notes At nominal input reference frequency C19i = 19.44 MHz
2
Lock Time
300
ms
Performance Characteristics: Output Jitter Generation - GR-253-CORE conformance (VCC = 3.3 V 10%;
TA = -40 to 85C)
GR-253-CORE Jitter Generation Requirements Jitter Measurement Filter 50 kHz - 80 MHz
Equivalent limit in time domain
ZL30416 Jitter Generation Performance Typ. 0.52 0.58 0.34 Max. 7.31 0.94 7.32 0.83 4.37 0.60
Interface (Category II) 1 OC-192 STS-192 OC-48 STS-48 OC-12 STS-12
Limit in UI 0.1 UIPP 0.01 UIRMS 0.1 UIPP 0.01 UIRMS 0.1 UIPP 0.01 UIRMS
Units psP-P psRMS psP-P psRMS psP-P psRMS
10.0 1.0 40.2 4.02 161 16.1
2
12 kHz - 20 MHz
3
12 kHz - 5 MHz
Typical figures are for design aid only: not guaranteed and not subject to production testing. Loop Filter components: RF=8.2 k, CF=470 nF.
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10%; TA = -40 to 85C)
Data Sheet
Performance Characteristics: Output Jitter Generation - G.813 conformance (Option 1 and 2) (VCC = 3.3 V ZL30416 Jitter Generation Performance
Equivalent limit in time domain
G.813 Jitter Generation Requirements Jitter Measurement Filter Option 1 1 STM-64 4 MHz to 80 MHz 0.1 UIpp 10.0 -
Interface
Limit in UI
Typ.
Max.
Units
6.95 0.89 11.5 1.04 6.40 0.68 8.67 1.06 3.33 0.42 19.1 2.88
psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS
0.49 20 kHz to 80 MHz 0.5 UIpp 50.2 0.82 2 STM-16 1 MHz to 20 MHz 0.1 UIpp 40.2 0.50 5 kHz to 20 MHz 0.5 UIpp 201 0.68 3 STM-4 250 kHz to 5 MHz 0.1 UIpp 161 0.26 1 kHz to 5 MHz 0.5 UIpp 804 1.51 Option 2 5 STM-64 4 MHz to 80 MHz 0.1 UIpp 10.0 0.49 20 kHz to 80 MHz 0.3 UIpp 30.1 0.82 6 STM-16 12 kHz - 20 MHz 0.1 UIpp 40.2 0.58 7 STM-4 12 kHz - 5 MHz 0.1 UIpp 161 0.34
Typical figures are for design aid only: not guaranteed and not subject to production testing. Loop Filter components: RF=8.2 k, CF=470 nF.
6.95 0.89 11.5 1.04 7.32 0.83 4.37 0.60
19
Zarlink Semiconductor Inc.
ZL30416
TA = -40 to 85C)
Data Sheet
Performance Characteristics: Output Jitter Generation - ETSI EN 300 462-7-1conformance (VCC = 3.3 V 10%; ZL30416 Jitter Generation Performance Typ. 0.50 5 kHz to 20 MHz 0.5UIpp 201 0.68 2 STM-4 250 kHz to 5 MHz 0.1 UIpp 161 0.26 1 kHz to 5 MHz 0.5 UIpp 804 1.51
Typical figures are for design aid only: not guaranteed and not subject to production testing. Loop Filter components: RF=8.2 k, CF=470 nF
EN 300 462-7-1 Jitter Generation Requirements Jitter Measurement Filter 1 MHz to 20 MHz
Equivalent limit in time domain
Interface 1 STM-16
Limit in UI 0.1 UIpp
Max. 6.40 0.68 8.67 1.06 3.33 0.42 19.1 2.88
Units psP-P psRMS psP-P psRMS psP-P psRMS psP-P psRMS
40.2
20
Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
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